Optimization of regeneration and transformation parameters in tomato and improvement of its salinity and drought tolerance

As part of our efforts to improve tomato tolerance to abiotic stress, we have undertaken this study to introduce two candidate genes encoding: a sodium antiporter and a vacuolar pyrophosphatase, previously shown to enhance drought and salt tolerance in transgenic Arabidopsis plants. First, we evaluated the potential of primary leaves from three to four week-old in vitro-grown tomato seedlings as alternative explants to cotyledons for tomato transformation. Our results demonstrated that primaryleaves are three times more efficient then cotyledons in terms of regeneration percentage, productivity, and transformation frequencies independently of the medium and genetic construct used. Second,primary leaves were used to introduce the genes of interest using Agrobacterium-mediated transformation. Many transgenic tomato plants were easily recovered. The presence of the transgenes and their expression were confirmed by PCR and RT-PCR analysis. The transformation frequencies for primary leaf explants ranged from 4 to 10% depending on the genetic construct used. The time requiredfrom inoculation of primary leaves with Agrobacterium cells to transfer of transgenic tomato plants to soil was only 2 months compared to 3 to 4 months using standard tomato transformation protocols. The transgenic tomato plants obtained in the current study were more tolerant to salinity and drought stress than their wild-type counterparts

Optimizations for real-time implementation of H264/AVC video encoder on DSP processor

International audienceReal-time H.264/AVC high definition video encoding represents a challenging workload to most existing programmable processors. The new technologies of programmable processors such as Graphic Processor Unit (GPU) and multicore Digital signal Processor (DSP) offer a very promising solution to overcome these constraints. In this paper, an optimized implementation of H264/AVC video encoder on a single core among the six cores of TMS320C6472 DSP for Common Intermediate Format (CIF) (352x288) resolution is presented in order to move afterwards to a multicore implementation for standard and high definitions (SD,HD).Algorithmic optimization is applied to the intra prediction module to reduce the computational time. Furthermore, based on the DSP architectural features, various structural and hardware optimizations are adopted to minimize external memory access. The parallelism between CPU processing and data transfers is fully exploited using an Enhanced Direct Memory Access controller (EDMA). Experimental results show that the whole proposed optimizations, on a single core running at 700 MHz for CIF resolution, improve the encoding speed by up to 42.91%. They allow reaching the real-time encoding 25 f/s without inducing any Peak Signal to Noise Ratio (PSNR) degradation or bit-rate increase and make possible to achieve real time implementation for SD and HD resolutions when exploiting multicore features

Fast Motion Estimation’s Configuration Using Diamond Pattern and ECU, CFM, and ESD Modes for Reducing HEVC Computational Complexity

The high performance of the high efficiency video coding (HEVC) video standard makes it more suitable for high-definition resolutions. Nevertheless, this encoding performance is coupled with a tremendous encoding complexity compared to the earlier H264 video codec. The HEVC complexity is mainly a return to the motion estimation (ME) module that represents the important part of encoding time which makes several researches turn around the optimization of this module. Some works are interested in hardware solutions exploiting the parallel processing of FPGA, GPU, or other multicore architectures, and other works are focused on software optimizations by inducing fast mode decision algorithms. In this context, this article proposes a fast HEVC encoder configuration to speed up the encoding process. The fast configuration uses different options such as the early skip detection (ESD), the early CU termination (ECU), and the coded block flag (CBF) fast method (CFM) modes. Regarding the algorithm of ME, the diamond search (DS) is used in the encoding process through several video resolutions. A time saving around 46.75% is obtained with an acceptable distortion in terms of video quality and bitrate compared to the reference test model HM.16.2. Our contribution is compared to other works for better evaluation

Clinical Study Prevalence and Impact of Anxiety and Depression on Type 2 Diabetes in Tunisian Patients over Sixty Years Old

Objectives. To estimate the prevalence of anxiety and depression using the Hospital Anxiety and Depression Scale (HADS) in a population aged over sixty years with type 2 diabetes and to study the impact of anxiety and depression on glycemic balance and disease outcome. Results. The prevalence of anxiety and depression in the 62 subjects included in the study was, respectively, 40.3% and 22.6%. We found a relationship between these disorders and complicated diabetes. The subjects having an imperfectly balanced diabetes had a higher average anxiety score than those having a good glycemic control (9.1 ± 4.2 versus 6.5 ± 3.1; = 0.017). No relationship was found between diabetes balance and depression. Conclusion. Association between anxiety and depressive disorders and diabetes is frequent and worsens patients' outcome, in terms of diabetes imbalance as well as in terms of diabetic complications. Our study shows that there is need for physicians to detect, confirm, and treat anxiety and depressive disorders in elderly diabetic patients

FPGA DESIGN FOR H.264/AVC ENCODER

International audienceIn this paper, we describe an FPGA H.264/AVC encoder architecture performing at real-time. To reduce the critical path length and to increase throughput, the encoder uses a parallel and pipeline architecture and all modules have been optimized with respect the area cost. Our design is described in VHDL and synthesized to Altera Stratix III FPGA. The throughput of the FPGA architecture reaches a processing rate higher than 177 million of pixels per second at 130 MHz, permitting its use in H.264/AVC standard directed to HDTV

An Efficient FPGA parallel Architecture for H.264/AVC Intra Prediction Algorithm

International audienceIn Motion Picture Experts Group (MPEG) and Video Coding Experts Group (VCEG) standards, intra prediction is used to eliminate the spatial redundancy. Given that the intra prediction stage is very complex in terms of computational effort, a hardware implementation on a re-configurable circuit is crucial for the requirements of different real-time multimedia applications. In this paper, we present novel hardware architecture for real-time implementation of intra prediction algorithm used in H.264 Advanced Video Coding (AVC) baseline profile video coding standard. This hardware is designed to be used as part of a complete H.264 video coding system for videoconference applications. We use an approach based on a novel organization of the intra prediction equations. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. On ALTERA Stratix II FPGA, the VHDL code is verified to work at 300 MHz for the luma intra prediction 4x4 architecture and 176 MHz for the luma intra prediction 16x16

Hardware architecture for H.264/AVC deblocking filter algorithm

International audienceThis paper presents novel hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264/AVC baseline profile video coding standard. This hardware is designed to be used as part of a complete H.264 video coding system for video conference applications. We use a novel edge filter ordering in a Macroblock to prevent the deblocking filter hardware from unnecessarily waiting for the pixels that will be filtered become available. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. The VHDL code is verified to work at 150 MHz in an ALTERA Stratix II FPGA

SW implementation of video coding using open virtual platform

International audienceThis paper demonstrates a new HardWare/SoftWare (HW/SW) verification method which simulates an entire embedded system. Our goal is to simulate the behavior of the HW/SW and verify that they are functioning correctly together. For that, we used an open virtual platform (OVP) made by Imperas Company, which allows programming, verifying and running application on the platform. We propose several implementations of the 16×16 intra prediction chain for the H264/AVC (Advanced Video Codec) encoder on MIPS32, ARM and PowerPC (PPC) processors. The results of the various implementations will be subject to discussio

An efficient hardware architecture for interpolation filter of HEVC decoder

International audienceIn most video coding standard, motion compensation MC is applied to remove temporal redundancy and reduce the size of bit stream significantly. In the decoder, the reconstructed MV (Motion Vector) is generated from the prediction error and neighboring information. However, due to the finite sampling the motion of blocks does not match exactly in the integer positions of samples grid. The High efficiency video coding standard HEVC introduced 7 taps filter and 8 taps filter for the interpolation of ¼ and ½ luminance sub positions respectively which can give a better precision in the inter prediction process. Furthermore, the profiling of the HM reference software proves that the interpolation filter consume more than 50% of the complexity of Motion Compensation block in the HEVC decoder with random access configuration. Therefore, a new flexible hardware architecture for half and quarter fractional pixels used in the interpolation filter is proposed in this paper. This architecture can process the whole fractional positions of 4×4 PU (prediction unit) in only 30 clock cycles and support a maximal throughput of QFHD@30fps at 185 MHZ. The implementation is performed with the technology TSMC 0.18 um